Dear experts, I noticed that commit a13f0d40eb0 compiler: delete arm backend) , does this mean that it is no longer possible to use Zig for embedded development with 32 bit arm devices?
It is possible to use Zig with 32-bit ARM devices. I think the commit refers to some attempt at building custom backend, instead of relying on LLVM.
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You can see the supported architectures in the release notes. This includes the “tiers” of support. If your architecture is on it, then it is supported to some degree. Like @lalinsky said, that commit removed an attempt at a custom backend for aarch64 before the release of 0.15.1. It has since been added back in. Note that it is targeted at aarch64, not 32 bit arm.
32 bit arm is supported by the llvm backend. Refer to the support table in the release notes for more information.
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Just because this confused me when I first started with Zig, an incredibly oversimplified explanation of what a “backend” means in this context:
Initially, a simplified view of the Zig compilation process for ALL platforms looked like:
Zig Code -> Lower to Zig AST -> Convert to LLVM AST -> LLVM Generates Machine Code (For instance, x86 CPU architecture instructions)
I’m definitely missing some steps and nuance in there, but it won’t be important for this explanation.
Many languages use LLVM as a “backend” for machine code generation since it allows you to not worry too much about the final hardware target of your code. As long as you can convert your code to LLVM’s “Abstract Syntax Tree”, LLVM will handle generating the actual machine code for you. However, LLVM can also be pretty slow, and due to having to conform to their specific AST can back you into some corners when designing your compiler.
So, Zig’s extremely ambitious long term goal is to write its own backend, entirely eliminating LLVM from the above process. So the new (again, oversimplified) process looks something like:
Zig Code -> Lower to Zig AST -> Zig Compiler Generates Machine Code
They already have this implemented for a number of platforms (see above table in release notes link), but 32 bit ARM targets are not yet one of them. However, this shouldn’t be confused with the compiler not supporting these targets. It does, it just doesn’t use the Zig backend for machine code generation.
`xtensa-freestanding` is an example of an MCU target (OG Espressif ESP32 chips that don’t use RISCV) that isn’t really supported by Zig. The best you got there is you can generate C code from Zig code using Zig’s compiler, and then compile that using Espressif’s Xtensa architecture specific compiler.
So, TLDR, for ARM MCUs you basically get whatever is currently supported by LLVM which is thankfully most mainstream ARM based MCUs!
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