Putting aside the smug ton, I like the solution he had for the problem.
I like that the register constraints are using Odin types, including vector types. Zig could use some improvement here. The "inout " syntax isn’t so clear in Odin though.
But I also abused Zig stringy ASM in the past for great success, like emitting PTX intrinsics or KVX assembly. Thoses aren’t Tier1 target for Zig and I don’t imagine they could receive such first class handling of their ISA.
The RexCode library providing full knowledge of how to encode/decode instructions is pretty cool. But I believe it’s mostly vibecoded, not that it matters IMO, for something so repetitive.
I’ve been waiting for something like this for what feels like ages.
The idea feels similar in spirit to parse inline assembly syntax according to a set of dialects; integrate inline assembly more closely with the zig language · Issue #10761 · ziglang/zig · GitHub, so I think it’s fair to say that it’s realistic Zig may get something comparable.
You can still assemble any instruction you like yourself without relying on the compiler
const code linksection(".text") = my_x86_64_assembler("xor rax, rax") catch @compileError("...");