# Everyone Says Assembly Is Untyped—Everyone Is Wrong - gingerBill **URL:** \ **Category:** Media\ **Created:** [August 21, 2026, 3:01am UTC](https://ziggit.dev/t/everyone-says-assembly-is-untyped-everyone-is-wrong-gingerbill/17311 "2026-08-21T03:01:32Z")\ **Posts on this page:** 5\ **Page:** 1
**Author:** ![Cloudef](https://ziggit.dev/user_avatar/ziggit.dev/cloudef/32/1370_2.png) [@Cloudef](https://ziggit.dev/u/Cloudef)\ **Post date:** [August 21, 2026, 3:01am UTC](https://ziggit.dev/t/everyone-says-assembly-is-untyped-everyone-is-wrong-gingerbill/17311/1 "2026-08-21T03:01:32Z")
> **[Everyone Says Assembly Is Untyped—Everyone Is Wrong - gingerBill](https://www.gingerbill.org/article/2026/08/20/designing-odins-inline-asm/)** > > TL;DR: I believe Odin's inline assembly is currently the best out of any language.The most important aspects are of this article listed below. I am not aware of any other assembly (GCC/Clang/Rust/Go...) that would combine all of these aspects:Inline... ---
**Author:** ![gwenzek](https://ziggit.dev/user_avatar/ziggit.dev/gwenzek/32/8137_2.png) [@gwenzek](https://ziggit.dev/u/gwenzek)\ **Post date:** [August 21, 2026, 6:28am UTC](https://ziggit.dev/t/everyone-says-assembly-is-untyped-everyone-is-wrong-gingerbill/17311/2 "2026-08-21T06:28:45Z")
Putting aside the smug ton, I like the solution he had for the problem. I like that the register constraints are using Odin types, including vector types. Zig could use some improvement here. The "inout " syntax isn’t so clear in Odin though. But I also abused Zig stringy ASM in the past for great success, like emitting PTX intrinsics or KVX assembly. Thoses aren’t Tier1 target for Zig and I don’t imagine they could receive such first class handling of their ISA. The [RexCode](https://github.com/odin-lang/Odin/tree/master/core/rexcode) library providing full knowledge of how to encode/decode instructions is pretty cool. But I believe it’s mostly vibecoded, not that it matters IMO, for something so repetitive. ---
**Author:** ![T0bee](https://ziggit.dev/user_avatar/ziggit.dev/t0bee/32/2037_2.png) [@T0bee](https://ziggit.dev/u/T0bee)\ **Post date:** [August 21, 2026, 7:47am UTC](https://ziggit.dev/t/everyone-says-assembly-is-untyped-everyone-is-wrong-gingerbill/17311/3 "2026-08-21T07:47:05Z")
I’ve been waiting for something like this for what feels like ages. The idea feels similar in spirit to [parse inline assembly syntax according to a set of dialects; integrate inline assembly more closely with the zig language · Issue #10761 · ziglang/zig · GitHub](https://github.com/ziglang/zig/issues/10761), so I think it’s fair to say that it’s realistic Zig may get something comparable. > [@gwenzek](#): > > But I also abused Zig stringy ASM in the past for great success, like emitting PTX intrinsics or KVX assembly. Thoses aren’t Tier1 target for Zig and I don’t imagine they could receive such first class handling of their ISA. You can still assemble any instruction you like yourself without relying on the compiler ```zig const code linksection(".text") = my_x86_64_assembler("xor rax, rax") catch @compileError("..."); ``` ---
**Author:** ![gwenzek](https://ziggit.dev/user_avatar/ziggit.dev/gwenzek/32/8137_2.png) [@gwenzek](https://ziggit.dev/u/gwenzek)\ **Post date:** [August 21, 2026, 9:28pm UTC](https://ziggit.dev/t/everyone-says-assembly-is-untyped-everyone-is-wrong-gingerbill/17311/4 "2026-08-21T21:28:16Z")
> [@T0bee](#): > > You can still assemble any instruction you want For some reason, I don’t find this option very compelling in a discussion about the ergonomic of inline assembly. It wasn’t a way saying it’s impossible to have a Zig version of this, but rather that Odin have it easy given they only support a few targets ---
**Author:** ![KilianHanich](https://ziggit.dev/user_avatar/ziggit.dev/kilianhanich/32/8254_2.png) [@KilianHanich](https://ziggit.dev/u/KilianHanich)\ **Post date:** [August 22, 2026, 2:38am UTC](https://ziggit.dev/t/everyone-says-assembly-is-untyped-everyone-is-wrong-gingerbill/17311/5 "2026-08-22T02:38:23Z")
Sure, Odin doesn’t support as many ISAs as Zig, but 1. The amount isn’t as big as it might seem at first (when you look at the output of `zig targets`, quite a few of the targets are just subvariants. And when you look at the [isa subdirectory of rexcode](https://github.com/odin-lang/Odin/tree/master/core/rexcode/isa) you see most of these merged (for example there’s 1 directory for all supported x86 targets; `zig targets` lists these as 3; or there’s 1 directory for RISC-V while `zig targets` lists these as 4 even if rexcode doesn’t support the Big Endian versions (like the Linux kernel) while Zig does). Sure, it’s still less than Zig, but not as extreme one might think at first. 2. At the end of the day, Zig needs an assembler for all of its targets anyways to target it. So developing the assembler information library first (which imo is always a good design principle) would essentially create Zig’s “rexcode” library.